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ne56605-42 system reset with built-in watchdog timer product data supersedes data of 2001 aug 22 2003 oct 15 integrated circuits
philips semiconductors product data ne56605-42 system reset with built-in watchdog timer 2 2003 oct 15 general description the ne56605-42 is designed to generate a reset signal, at a threshold voltage of 4.2 v, for a variety of microprocessor and logic systems. accurate reset signals are generated during momentary power interruptions, or whenever power supply voltages sag to intolerable levels. the ne56605-42 has a built-in watchdog timer to monitor the microprocessor and ensure it is operating properly. any abnormal system operations due to microprocessor malfunctions are terminated by the watchdog's generating a system reset. the ne56605-42 has a watchdog monitoring time of 10 ms (typical). the ne56605-42 is offered in the 8-lead small outline surface mount package (sop005). features ? both positive and negative logic reset output signals are available ? accurate threshold detection ? internal power-on reset delay ? internal watchdog timer programmable with external capacitor ? watchdog monitoring time of 10 ms ? reset assertion with v cc down to 0.8 v dc (typical) ? few external components required. applications ? microcomputer systems ? logic systems. simplified system diagram sl01282 reset generator programmable watchdog timer 3 clk 2 reset 8 reset 1 c t v ref 4 gnd r 7 r c v s 6 wd c v cc 5 gnd clk reset reset logic system ne56605-42 figure 1. simplified system diagram. ordering information type number package temperature type number name description version range NE56605-42D so8 plastic small outline package; 8 leads; body width 3.9 mm sop005 20 to +70 c
philips semiconductors product data ne56605-42 system reset with built-in watchdog timer 2003 oct 15 3 part number marking the package is marked with a four letter code in the first line to the right of the logo. the first three letters designate the product. the fourth letter, represented by `x', is a date tracking code. the remaining two or three lines of characters are internal manufacturing codes. 2 3 1 5 4 6 7 8 part number marking ne56605-42 a a e x pin configuration sl01279 1 2 3 4 8 7 6 5 top view c t reset clk gnd reset v s wd c v cc ne56605-42 figure 2. pin configuration. pin description pin symbol description 1 c t t wdm , t wdr , t pr adjustment pin. t wdm , t wdr , t pr times are dependent on the value of external c t capacitor used. see figure 18 (timing diagram) for definition of t wdm , t wdr , t pr times. 2 reset reset high output pin. 3 clk clock input pin from logic system for watchdog timer. 4 gnd circuit ground. 5 v cc power supply pin for circuit. 6 wd c watchdog timer control pin. the watchdog timer is enabled when this pin is unconnected, and disabled when this pin is connected to ground. 7 v s detection threshold adjustment pin. the detection threshold can be increased by connecting this pin to v cc with a pull-up resistor. the detection threshold can be decreased by connecting this pin to ground with a pull-down resistor. 8 reset reset low output pin. maximum ratings symbol parameter min. max. unit v cc power supply voltage 0.3 10 v v s v s pin voltage 0.3 10 v v clk clk pin voltage 0.3 10 v v oh reset and reset pin voltage 0.3 10 v t oper operating temperature 20 70 c t stg storage temperature 40 125 c p power dissipation 250 mw
philips semiconductors product data ne56605-42 system reset with built-in watchdog timer 2003 oct 15 4 dc electrical characteristics characteristics measured with v cc = 5.0 v, and t amb = 25 c, unless otherwise specified. see figure 23 (test circuit 1) for test configuration used for dc parameters. symbol parameter conditions min. typ. max. unit i cc supply current during watchdog timer operation 0.7 1.0 ma v sl reset detection threshold v s = open; v cc = falling 4.05 4.20 4.35 v v sh reset detection threshold v s = open; v cc = rising 4.15 4.30 4.45 v d v s / d t amb temperature coefficient of reset threshold 20 c t amb 70 c 0.01 %/ c v hys reset threshold hysteresis v hys = v sh (rising v cc ) v sl (falling v cc ) 50 100 150 mv v th clk input threshold 0.8 1.2 2.0 v i ih clk input current, high-level v clk = 5.0 v 0 1.0 m a i il clk input current, low-level v clk = 0 v 20 10 3.0 m a v oh1 output voltage, high-level i reset = 5.0 m a; v s = open 4.5 4.8 v v oh2 i reset current = 5.0 ma; v s = 0 v 4.5 4.8 v v ol1 output voltage, low-level i reset = 3.0 ma; v s = 0 v 0.2 0.4 v v ol2 i reset = 10 ma; v s = 0 v 0.3 0.5 v v ol3 i reset = 0.5 ma; v s = open 0.2 0.4 v v ol4 i reset = 1.0 ma; v s = open 0.3 0.5 v i ol1 output sink current v reset = 1.0 v; v s = 0 v 10 16 ma i ol2 v reset = 1.0 v; v s = open 1.0 2.0 ma i ct1 c t charge current v ct = 1.0 v; wd c = open during watchdog operation 8 12 24 m a i ct2 v ct = 1.0 v; during power-on reset operation 0.8 1.2 2.4 m a v ccl1 supply voltage to assert reset operation v reset = 0.4 v; reset current = 0.2 ma 0.8 1.0 v v ccl2 v reset = v cc 0.1 v; 1 m w resistor (pin 2 to gnd) 0.8 1.0 v
philips semiconductors product data ne56605-42 system reset with built-in watchdog timer 2003 oct 15 5 ac electrical characteristics characteristics measured with v cc = 5.0 v, and t amb = 25 c, unless otherwise specified. see figure 24 (test circuit 2) for test configuration used for ac parameters. symbol parameter conditions min. typ. max. unit t p1 minimum power supply pulse width for detection 4.0 v negative-going v cc pulse 5.0 v 8.0 m s t clkw clock input pulse width 3.0 m s t clk clock input cycle 20 m s t wdm watchdog monitoring time (notes 1, 6) c t = 0.1 m f; r ct = open 5.0 10 15 ms t wdr watchdog reset time (notes 2, 6) c t = 0.1 m f 1.0 2.0 3.0 ms t pr power-on reset delay time (notes 3, 6) v cc = rising from 0 v; c t = 0.1 m f 50 100 150 ms t pd1 reset, reset propagation delay time (note 4) reset : r l1 = 2.2 k w ; c l1 = 100 pf 2.0 10 m s t pd2 (n o t e 4) reset: r l2 = 10 k w ; c l2 = 20 pf 3.0 10 m s t r1 reset, reset rise time (note 5) reset : r l1 = 2.2 k w ; c l1 = 100 pf 1.0 1.5 m s t r2 reset: r l2 = 10 k w ; c l2 = 20 pf 1.0 1.5 m s t f1 reset, reset fall time (note 5) reset : r l1 = 2.2 k w ; c l1 = 100 pf 0.1 0.5 m s t f2 reset: r l2 = 10 k w ; c l2 = 20 pf 0.5 1.0 m s notes: 1. `watchdog monitoring time' is the duration from the last pulse (negative-going edge) of the timer clear clock pulse until res et output pulse occurs (see figure 18). a reset signal is output if a clock pulse is not input during this time. 2. `watchdog reset time' is the reset pulse width (see figure 18). 3. `power-on reset delay time' is the duration measured from the time v cc exceeds the upper detection threshold (v sh ) and power-on reset release is experienced (reset output high; reset output low). 4. `reset, reset propagation delay time' is the duration from when the supply voltage sags below the lower detection threshold (v sl ) and reset occurs (reset output low, reset output high). 5. reset, reset rise and fall times are measured at 10% and 90% output levels. 6. watchdog monitoring time (t wdm ), watchdog reset time (t wdr ), and power-on reset delay time (t pr ) during power-on can be modified by varying the c t capacitance. the times can be approximated by applying the following formula. the recommended range for c t is 0.001 m f to 10 m f. formula 1. calculation for approximate t pr , t wdm , and t wdr values: t pr (ms) 1000 c t ( m f) t wdm (ms) 100 c t ( m f) t wdr (ms) 20 c t ( m f) example: when c t = 0.1 m f and wd c = open: t pr 100 ms t wdm 10 ms t wdr 2.0 ms
philips semiconductors product data ne56605-42 system reset with built-in watchdog timer 2003 oct 15 6 typical performance curves sl01303 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 0 0.8 0.6 0.4 0.2 1.4 1.0 1.2 with clock signals to watchdog without clock signals to watchdog v cc , power supply voltage (v) i cc power supply current (ma) t amb = 35 c figure 3. power supply current versus voltage. sl01304 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 0 6.0 4.0 3.0 2.0 1.0 5.0 t amb = 25 c, 25 c, 75 c v ol v sh v sl reset pull-up r = 10 k w v cc , power supply voltage (v) v rst , reset output voltage (v) figure 4. reset output voltage versus supply voltage. sl01302 0 1.0 2.0 3.0 4.0 5.0 6.0 0 1.0 2.0 3.0 4.0 5.0 6.0 v cc power supply voltage (v) v rst , reset output voltage (v) reset pull-up r = 2.2 k w t amb = 25 c t amb = 25 c t amb = 75 c v ol v sl v sh figure 5. reset output voltage versus supply voltage. sl01301 v sl , v t amb , ambient temperature ( c) v cc = rising (v sh ) v cc = falling (v sl ) , detection threshold (v) sh 4.5 4.4 4.3 4.2 4.1 4.0 40 20 0 20 40 60 80 100 v sh v sl figure 6. detection threshold versus temperature. sl01300 v ol , reset output saturation (mv) i ol , reset output sink current (ma) 0 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 600 500 400 300 200 100 0.2 0.4 t amb = 25 c t amb = 75 c v cc = 5.0 v reset pull-up r = 10 k w t amb = 25 c figure 7. reset saturation versus sink current. sl01299 v ol , reset output saturation (mv) i ol , reset output sink current (ma) 0 6 8 10 12 14 16 18 0 600 500 400 300 200 100 2 4 v cc = 5.0 v reset pull-up r = 2.2 k w t amb = 25 c t amb = 75 c t amb = 25 c figure 8. reset saturation versus sink current.
philips semiconductors product data ne56605-42 system reset with built-in watchdog timer 2003 oct 15 7 sl01298 v om , reset high level output (v) i om , reset high output leakage current ( m a) v cc = 5.0 v t amb = 25 c 4.0 5.2 5.0 4.8 4.6 4.4 4.2 0 2 4 6 8 10 12 14 16 18 figure 9. reset high-level voltage versus current. sl01297 v om , reset high level output (v) i om , reset high output leakage current ( m a) 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 0 2.0 4.0 6.0 8.0 10 16 14 12 v cc = 5.0 v t amb = 25 c figure 10. reset high-level voltage versus current. sl01296 40 20 60 80 100 t amb , ambient temperature ( 5 c) 120 140 100 80 60 40 20 0 v cc = 5.0 v c t = 0.1 m f r ct = open t pr , power-on reset hold (ms) figure 11. poweron reset hold time versus temperature. sl01295 40 20 60 80 100 t amb , ambient temperature ( 5 c) 120 140 100 80 60 40 20 0 v cc = 5.0 v c t = 0.1 m f r ct = open t wdm , watchdog monitoring (ms) figure 12. watchdog monitoring time versus temperature. sl01294 t wdr , watchdog reset (ms) 040 1.5 100 80 60 20 20 40 1.0 2.0 2.5 3.0 v cc = 5.0 v c t = 0.1 m f t amb , ambient temperature ( c) figure 13. watchdog reset time versus temperature.
philips semiconductors product data ne56605-42 system reset with built-in watchdog timer 2003 oct 15 8 sl01290 v cc = 5.0 v t amb = 25 c 10 3 10 2 10 1 1.0 10 1.0 10 10 2 10 3 10 4 t pr , power-on reset hold (ms) c t , capacitance ( m f) figure 14. power-on reset hold time versus c t . sl01291 v cc = 5.0 v t amb = 25 c 10 3 10 2 10 1 1.0 10 10 2 10 1 1.0 10 10 2 t wdr , watchdog reset (ms) c t , capacitance ( m f) figure 15. watchdog reset time versus c t . sl01292 v cc = 5.0 v t amb = 25 c 10 3 10 2 10 1 1.0 10 10 1 1.0 10 10 2 10 3 t wdm , watchdog monitoring (ms) c t , capacitance ( m f) figure 16. watchdog reset time versus c t .
philips semiconductors product data ne56605-42 system reset with built-in watchdog timer 2003 oct 15 9 technical description general discussion the ne56605-42 combines a watchdog timer and an undervoltage reset function in a single so8 surface mount package. this provides a space-saving solution for maintaining proper operation of typical 5.0 volt microprocessor-based logic systems. either function, or both, can force the microprocessor into a reset. while the watchdog monitors the microprocessor operation, the undervoltage reset monitors the supply voltage to the microprocessor. if the microprocessor clock signal ceases or becomes erratic, the ne56605-42 outputs a reset signal to the microprocessor. if the microprocessor supply voltage sags to 4.2 volts or less, the ne56605-42 outputs a reset signal for the duration of the supply voltage deficiency. the undervoltage reset signal allows the microprocessor to shut down in an orderly manner to avoid system corruption. in addition to a single reset output, the ne56605-42 has complementary reset and reset outputs for system use. the undervoltage detection threshold incorporates hysteresis to prevent generating erratic resets. the watchdog timer requires a pulse input. normally this signal comes from the system microprocessor's clock. for operation, an external capacitor (c t ) must be connected from pin 1 to ground. normally a 0.1 m f capacitor is used for c t . the c t capacitor and a fixed internal resistance establish the required minimum frequency of watchdog input signal for the device to not output a reset signal. in the absence of a watchdog input pulse, the c t capacitor charges to the 0.2 volt threshold of the internal comparator, causing a reset signal to be output. if microprocessor clock signals are received within the required interval, no watchdog reset signal will be output. grounding the watchdog control pin (wd c , pin 6) disables the watchdog function. removing the ground from pin 6, allowing it to float, enables the watchdog function. enabling or disabling the watchdog function has no effect on the undervoltage detection function. although the temperature coefficient of detection threshold is specified over a temperature of 20 c to +70 c, the device will support operation in excess of this temperature range. see the supporting curves for performance over the full temperature range of 30 c to +85 c. some degradation in performance will be experienced at the temperature extremes and the system designer should take this into account. sl01293 8 4 3 s q r 7 5 sq r sq r 2 reset reset 1c t 6 gnd wd c pulse generator r r r 47 k w 12 m a 0.1 v 1.2 m a 1.2 m a r r 8.2 k w 0.2 v r r 54 k w r 26 k w c v cc c p figure 17. functional diagram.
philips semiconductors product data ne56605-42 system reset with built-in watchdog timer 2003 oct 15 10 timing diagram the timing diagram shown in figure 18 depicts the operation of the device. letters indicate events on the time axis. a: at start-up `a', the v cc and reset voltages begin to rise. also the reset voltage initially rises, but then abruptly returns to a low state. this is due to v cc reaching the level (approximately 0.8 v) that activates the internal bias circuitry, asserting reset . b: just before `b', the c t voltage starts to ramp up. this is caused by, and coincident to, v cc reaching the threshold level of v sh . at this level the device is in full operation. the reset output continues to rise as v cc rises above v sh . this is normal. c: at `c', v cc is above the undervoltage detect threshold, and c t has ramped up to its upper detect level. at this point, the device removes the hold on the resets. reset goes high while reset goes low. also, an internal ramp discharge transistor activates, discharging c t . in a microprocessor-based system these events remove the reset from the microprocessor, allowing it to function normally. the system must send clock signals to the watchdog timer often enough to prevent c t from ramping up to the c t threshold, to prevent reset signals from being generated. each clock signal discharges c t . cd: midway between `c' and `d', the clk signals cease allowing the c t voltage to ramp up to its upper threshold at `d'. at this time, reset signals are generated (reset goes low; reset goes high). the device attempts to come out of reset as the c t voltage is discharged and finally does come out of reset when clk signals are re-established after two attempts of c t . ef: immediately before `e', falling v cc causes the reset signal to sag. clk signals are still being received, c t is within normal operating range, and reset signals are not output. v cc continues to sag until the v sl undervoltage threshold is reached. at that time, reset signals are generated (reset goes low; reset goes high). at `e', v cc starts to rise, and the reset voltage rises with v cc . however, c t voltage does not start to ramp up until `f' when v cc reaches the v sh upper threshold. g: the reset outputs are released at `g' when c t reaches the upper threshold level again. after `g', normal clk signals are received, but at a lower frequency than those following event `c'. the frequency is above the minimum frequency required to keep the device from outputting reset signals. gh: at `h', v cc is normal, clk signals are being received, and no reset signals are output. at event `h', the v cc starts falling, causing reset to also fall. j: at event `j', v cc sags to the point where the v sl undervoltage threshold point is reached, and at that level reset signals are output (reset to a low state, and reset to a high state). as the v cc voltage falls lower, the reset voltage falls lower. k: at event `k', the v cc voltage has deteriorated to a level where normal internal circuit bias is no longer able to maintain a reset , and as a result may exhibit a slight rise to something less than 0.8 v. as v cc decays even further, reset also decreases to zero. sl01283 time v sh v sl v cc c tthresh c t reset ab c d ef g hjk t wdr t wdm t pr t clk clk 0.8 v reset figure 18. timing diagram.
philips semiconductors product data ne56605-42 system reset with built-in watchdog timer 2003 oct 15 11 application information the detection threshold voltage can be adjusted by externally influencing the internal divider reference voltage. figures 19 and 21 show a method to lower and raise the threshold voltage. figures 20 and 22 show the influence of the pull-down and pull-up resistors on the threshold voltage. the use of a capacitor (1000 pf or larger) from pin 7 to ground is recommended to filter out noise from being imposed on the threshold voltages. the reset detection threshold can be decreased by connecting an external resistor r 1 from pin 7 to v cc , as shown in figure 19. see figure 20 to determine the approximate value of r 1 to use. the reset detection threshold can be increased by connecting an external resistor r 2 from pin 7 to ground, as shown in figure 21. see figure 22 to determine the approximate value of r 2 to use. sl01286 1 2 3 4 8 7 6 5 reset reset clk gnd logic system 1000 pf ne56605-42 v cc r 1 figure 19. circuit to lower detection threshold. sl01289 5.0 4.0 3.5 3.0 0 100 200 300 400 500 600 700 r 1 , external pin 7 to v cc resistor (k w ) vs, reset detection threshold (v) v cc = 5.0 v t amb = 25 c c t = 0.1 m f v sh v sl figure 20. reset detection threshold versus external r 1 . sl01287 1 2 3 4 8 7 6 5 reset reset clk gnd logic system 1000 pf ne56605-42 v cc r 2 figure 21. circuit to raise detection threshold. sl01288 5.1 5.0 4.9 4.8 4.7 4.6 4.5 4.4 4.3 v cc = 5.0 v t amb = 25 c c t = 0.1 m f 0 100 200 300 400 500 600 700 r 2 , external pin 7 to ground resistor (k w ) vs, reset detection threshold (v) v sh v sl figure 22. reset detection threshold versus external r 2 .
philips semiconductors product data ne56605-42 system reset with built-in watchdog timer 2003 oct 15 12 parametric testing dc and ac characteristics can be tested using the circuits shown in figures 23 and 24. associated switch and power supply settings are shown in table 1 and table 2, respectively. sl01284 4 2 v crt 3 1 8 v crt abc 6 5 a 7 a a a a s 5 0.1 m f i cc v cc s 6 s 7 v clk v o2 crt 2 i clk i o2 i ct s 4 i reset r 1.0 m w v ct s 3 i reset crt 1 v o0 s 1 v o1 s 2 1000 pf reset v s r ct v cc c t reset clk gnd i o1 a b c figure 23. test circuit 1 (dc parameters). table 1. dc characteristics test circuit 1 switch and power supply settings parameter symbol s 1 s 2 s 3 s 4 s 5 s 6 s 7 v cc v clk v ct i reset i reset read power supply current i cc b off off b off on on 5.0 v 5.0 v 0 v i cc reset threshold (low) (note 1) v sl b off off b on on on 5.0 to 4.0 v 3.0 v 3.0 v v o1 , crt 1 reset threshold (high) (note 2) v sh b off off b on on on 4.0 to 5.0 v 3.0 v 3.0 v v o1 , crt 1 clock input threshold (note 3) v th b off off b off on on 5.0 v 0 to 3.0 v 1.0v i clk clock input current (high) i th b off off b off on on 5.0 v 5.0 v 0 v i clk clock input current (low) i tl b off off b off on on 5.0 v 0 v 0 v i clk reset output voltage (high) v oh1 b off on b on on on 5.0 v 5.0 v 3.0 v 5.0 m a v o1 v oh2 b on off c on on on 5.0 v 5.0 v 3.0 v 5.0 m a v o2 reset output voltage (low) v ol1 b on on b on on on 5.0 v 5.0 v 3.0 v 3.0 ma v o1 v ol2 b on on b on on on 5.0 v 5.0 v 3.0 v 10 ma v o1 v ol3 b off off c on on on 5.0 v 5.0 v 3.0 v 0.5 ma v o2 v ol4 b off off c on on on 5.0 v 5.0 v 3.0 v 1.0 ma v o2 reset output sink current (n t 4) i ol1 c on off b on on on 5.0 v 5.0 v 3.0 v i o1 (note 4) i ol2 a off off b on on on 5.0 v 5.0 v 3.0 v i o2 c t charge current 1 i ct1 b off off b off off on 5.0 v 1.0 v i ct c t charge current 2 i ct2 b off off b on off on 5.0 v 1.0 v i ct minimum power supply for reset (note 5) v ccl1 b off on b on on on 0 to 2.0 v 0 v 0 v v o1 , v cc minimum power supply for reset (note 6) v ccl2 b on off a on on on 0 to 2.0 v 0 v 0 v v o2 , v cc notes: 1. decrease v cc from 5.0 v to 4.0 v and note the v cc value when v o1 (observed on crt 1 ) transitions to an abrupt low state. 2. increase v cc from 4.0 v to 5.0 v and note the v cc value when v o1 (observed on crt 1 ) transitions to an abrupt high state. 3. increase the clock voltage (v clk ) from 0 v to 3.0 v and observe the value of v clk when i clk transitions to an abrupt increase. 4. measured with v o0 = 1.0 v. 5. increase v cc from 0 v to 2.0 v and note the v cc value when v o1 (observed on crt 1 ) transitions to an abrupt low state. the v o1 value will initially track the v cc voltage increase until the internal circuit bias becomes active, at which time the v o1 value will return to a low state. 6. increase v cc from 0 v to 2.0 v and note the v cc value when v o2 (observed on crt 2 ) starts to track the v cc voltage.
philips semiconductors product data ne56605-42 system reset with built-in watchdog timer 2003 oct 15 13 sl01285 8 6 5 7 crt 20pf crt ac b ac b 4 2 3 1 crt crt v clka crt 3 v clk s 2 v cca r 10 k w crt 2 0.1 m f c t reset clk gnd crt 4 s 1 v cc r ct v s reset v cc r 2.2 k w 100 pf crt 1 figure 24. test circuit 2 (ac parameters). table 2. switch and power supply settings, ac parameters parameter symbol s 1 s 2 v cca v cc v clka v clk crt v cc pulse width for detection (note 1) t p1 c c 5.0 v 4.0 v t 1 t 2 1.4 v 0 v t 3 1, 2, 3 clock input pulse width (note 2) t clkw a c 5.0 v t 2 1.4 v 0 v t 2 1, 2, 3 clock input cycle (note 3) t clk a c 5.0 v t 2 1.4 v 0 v t 3 1, 2, 3 watchdog monitoring time t wdm a a 5.0 v 5.0 v 1, 2, 3 watchdog reset time t wdr a a 5.0 v 5.0 v 1, 2, 3 power-on reset delay time t pr b to a a 5.0 v 5.0 v 1, 2, 3 reset, reset propagation delay time t pd1 c b 5.0 v 4.0 v 0 v 1, 2 t pd2 c b 5.0 v 4.0 v 0 v 2, 3 reset, reset rise time t r1 a a 5.0 v 5.0 v 1 t r2 a a 5.0 v 5.0 v 3 reset, reset fall time t f1 a a 5.0 v 5.0 v 1 t f2 a a 5.0 v 5.0 v 3 notes: 1. t 1 = 8.0 m s. 2. t 2 = 3.0 m s. 3. t 3 = 20 m s.
philips semiconductors product data ne56605-42 system reset with built-in watchdog timer 2003 oct 15 14 packing method the ne56605-42 is packed in reels, as shown in figure 25. sl01305 tape detail cover tape carrier tape reel assembly tape guard band barcode label box figure 25. tape and reel packing method
philips semiconductors product data ne56605-42 system reset with built-in watchdog timer 2003 oct 15 15 so8: plastic small outline package; 8 leads; body width 3.9 mm sop005
philips semiconductors product data ne56605-42 system reset with built-in watchdog timer 2003 oct 15 16 revision history rev date description _3 20031015 product data (9397 750 12123). ecn 853-2251 30310 of 08 september 2003. supersedes data of 2001 aug 22 (9397 750 08733). modifications: ? change package outline version to sop005 in ordering information table and package outline sections. _2 20010822 product data (9397 750 08733). ecn 853-2251 26949 of 22 august 2001. supersedes data of 2001 apr 24. definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed i nformation see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the l imiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any o ther conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affec t device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors ma ke no representation or warranty that such applications will be suitable for the specified use without further testing or modificatio n. disclaimers life support e these products are not designed for use in life support appliances, devices, or systems where malfunction of these products ca n reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applica tions do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes in the productseincluding circuits, standard cells, and/or softwaree described or contained herein in order to improve design and/or performance. when the product is in full production (status `production') , relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for th e use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranti es that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . ? koninklijke philips electronics n.v. 2003 all rights reserved. printed in u.s.a. date of release: 10-03 document order number: 9397 750 12123

data sheet status [1] objective data preliminary data product data product status [2] [3] development qualification production definitions this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the specification in any manner without notice. this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change notification (cpcn). data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level i ii iii

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